Digital-to-analog converter switching circuitry

ABSTRACT

A digital-to-analog conversion circuit includes first and second DACs. Switch circuitry couples a selected output of only one of the DACs to an output node at any given time. In one embodiment, a second output of the first DAC is coupled to the first output of the second DAC at a common node. The first output of the first DAC is coupled to a first switch node and a second output of the second DAC is coupled to a second switch node. A first switch couples the common node to the first switch node in response to a first switch signal. A second switch couples the common node to the second switch node in response to a second switch signal. The switch signals ensure that the common node is coupled through the first and second switches to only one of the first and second switch nodes at any given time.

FIELD OF THE INVENTION

[0001] This invention relates to the field of digital-to-analogconverter circuitry. In particular, this invention is drawn to methodsand apparatus for reducing glitches and extraneous noise indigital-to-analog converter circuitry.

BACKGROUND OF THE INVENTION

[0002] Digital-to-analog converter (DAC) circuitry is used in numerouselectronics application. A DAC requires a finite amount of time to senseinput codes and convert the codes to an analog value (e.g., current orvoltage) that the DAC then provides at its output. A finite amount oftime is also required for the output of the DAC to stabilize or settleupon the analog value. These time elements establish an upper boundaryon the performance bandwidth of the digital-to-analog conversionprocess.

[0003] A current steering DAC architecture is particularly desirable forspeed advantages over other architectures. A current steering DACgenerates a differential current output that is typically applied to acurrent-to-voltage converting amplifier to produce a differentialvoltage output. Current steering DACs, however, tend to have relativelypoor dynamic performance.

[0004] Transient voltages will appear at the DAC output due to theperiodic code updates applied to the DAC. Although the effect isdependent upon the specific DAC architecture, the transients frequentlymanifest as a “smearing” of the analog output. This smearing canintroduce distortion in a baseband signal even after application of areconstruction filter. More succinctly, input code transitions forcurrent steering DACs frequently result in a “glitch” in the outputsignal.

[0005] Various attempts have been made to reduce or eliminate the glitchfor current steering DACs. Generally, the attempts focus on reducing theheight or the width of glitch.

[0006] For example, one current steering DAC architecture usesthermometer encoding for the DAC internal current sources. Although thisapproach ensures that the height of the glitch is less than the smallestDAC current step size, one disadvantage of such an architecture is that2^(N) current sources are required, where N is the number of bits ofresolution.

[0007] Another approach is to use a row of latches to resynchronize theedges of the input binary codes at the DAC input such that the delaysbetween different codes are minimized. This approach attempts to reducethe width of the glitch. Aside from noise and area impact, this approachdoes not fully eliminate the glitch due to the residual mismatch inlatch gate delays and DAC switches.

SUMMARY OF THE INVENTION

[0008] In view of limitations of known systems and methods, methods andapparatus for controlling digital-to-analog conversion circuitry aredisclosed.

[0009] One digital-to-analog conversion circuit includes first andsecond digital-to-analog converters (DACs). Switch circuitry couples aselected output of each DAC to an output node. The switch circuitrycouples the selected output of only one of the first and second DACs tothe output node at any given time. In one embodiment, the switchcircuitry couples the differential output of a selected exclusive one ofthe first and second DACs to a pair of output nodes. In one embodiment,when the differential output of the selected DAC is coupled to theoutput node pair, the differential output of the non-selected DAC iscoupled to a throwaway node.

[0010] One embodiment of a sampling apparatus includes a first and asecond digital to analog converter (DAC). Each DAC has a first and asecond output. The second output of the first DAC is coupled to thefirst output of the second DAC at a common node. The first output of thefirst DAC is coupled to a first switch node and a second output of thesecond DAC is coupled to a second switch node. The apparatus includes afirst switch for coupling the common node to the first switch node and asecond switch for coupling the common node to the second switch node.

[0011] The first switch couples the common node to the first switch nodein response to a first switch signal. The second switch couples thecommon node to the second switch node in response to a second switchsignal. In one embodiment, active regions of the first and second switchsignals do not overlap to ensure that the common node is coupled throughthe first and second switches to only one of the first and second switchnodes at any given time.

[0012] In one embodiment the first and second switch nodes are connectedto input nodes of a differential amplifier. In an alternativeembodiment, the sampling apparatus further comprises buffer circuitrywherein the first and second switch nodes are coupled to the input nodesof the differential amplifier through the buffer circuitry.

[0013] In various embodiments the DACs, switches, buffer circuitry, anddifferential amplifier may be fabricated on an integrated circuit diesuch that they share a common semiconductor substrate within anintegrated circuit package. The integrated circuit package may furtherinclude a power amplifier for driving external analog circuitry such asa telephone subscriber line.

[0014] Other features and advantages of the present invention will beapparent from the accompanying drawings and from the detaileddescription that follows below.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present invention is illustrated by way of example and notlimitation in the figures of the accompanying drawings, in which likereferences indicate similar elements and in which:

[0016]FIG. 1 illustrates an embodiment of a two DAC sampling system.

[0017]FIG. 2 illustrates one embodiment of buffering circuitry for theDAC circuitry of FIG. 1.

[0018]FIG. 3 illustrates a one embodiment of an improved two DACsampling system.

[0019]FIG. 4 illustrates one embodiment the improved two DAC samplingsystem further incorporating the buffering circuitry of FIG. 2.

[0020]FIG. 5 illustrates a function block diagram of a two DAC samplingsystem fabricated on a common semiconductor substrate.

DETAILED DESCRIPTION

[0021]FIG. 1 illustrates one embodiment of circuitry for adigital-to-analog conversion system. Glitches in the output of the DACscan occur for a number of reasons. The inputs, for example, may notarrive at precisely the same time (inter-bit delay). The processing ofsome bits may take longer than others (intra-bit delay). The result isthat the outputs of the DACs will have glitches due to transitions ininput codes. The glitches tend to be differential in nature such thatthe same glitch signal of opposite sign appears at each output of agiven DAC. The differential glitch will be exacerbated if the glitch ispresent on the input nodes of a differential amplifier coupled to theDAC output.

[0022] In order to reduce glitches in any input signals to differentialamplifier 150 due to the updating of the DAC, two DACS are used withswitching circuitry designed to provide the output of one DAC while theother is being updated. The use of two DACs switched in this manneravoids having the transients or glitches resulting from changes in codesinput to the DACs appear at the input nodes of differential amplifier.

[0023] In one embodiment, each DAC (110, 130) produces a differentialcurrent output that is applied to a current-to-voltage convertingamplifier 150 to produce a differential voltage V_(OUT). Each DAC isdesigned so that the sum of its output currents is substantiallyconstant regardless of the applied inputs. Thus, for example, I₁₁+I₁₂and I₂₁+I₂₂ are substantially constant although the individual currentsmay vary considerably. Such DAC architectures are frequently referred toas current steering DACs.

[0024] The dual DAC system uses a two phase clock (φ₁, φ₂) Switches 112,114, 116, and 118 switch the outputs of DAC1 between the input ofcurrent-to-voltage differential amplifier 150 and a bias voltage node(V_(BIAS) 120). Similarly, switches 132, 134, 136, and 138 switch theoutputs of DAC2 between the input of current-to-voltage amplifier 150and the bias voltage node 120. Switches 112-118 and 132-138 may also bereferred to individually as commutators and collectively as commutationcircuitry.

[0025] When φ₁ is active, switches 112 and 116 couple the outputs ofDAC1 to the input of the current-to-voltage amplifier 150 at nodes 152and 154. At the same time, the outputs of DAC2 are coupled to the samebias voltage node 120 (and thus each other) through switches 134 and138. Thus when φ₁ is active, V_(OUT) corresponds to the output of DAC1.

[0026] When φ₂ is active, switches 132 and 136 couple the outputs ofDAC2 to the input of the current-to-voltage amplifier 150 at nodes 152and 154. At the same time, the outputs of DAC1 are coupled to the samebias voltage node 120 (and thus each other) through switches 114, and118.

[0027] The two phase clock signal 170 includes φ₁ 172 and φ₂ 174. In theillustrated embodiment, each switch is controlled directly by one phaseof the two phase clock signal 170. Thus the switch control signals areindependent of the value of any DAC input code (i.e., data). The twophase clock is designed so that the active regions of each signal do notoverlap. This ensures that at most one DAC is coupled to provide itsoutputs to the current-to-voltage amplifier at any given time. Theswitch circuitry thus couples a differential output of a selectedexclusive one of the first and second DACs to the output node pair 152and 154.

[0028] Typically, φ₁ and φ₂ are derived from a master clock signalappearing in the same integrated circuit. A two phase clock generator,for example, can be used to generate a multiphase clock signal from themaster clock signal. As a result of the multiphase clock signal and theswitching circuitry, the analog signal at output node pair 152 and 154is effectively a time interleaved analog signal generated bymultiplexing the differential outputs of DAC1 and DAC2.

[0029] The bias voltage voltage node 120 serves effectively as a“throwaway” node. The “glitches” are not actually removed from theoutput of any DAC. Instead, the switching circuitry ensures that theglitches are re-directed to a throwaway node which is entirelyindependent of the inputs of the differential amplifier 150. The biasvoltage V_(BIAS) is adjusted to be at substantially the same potentialas the virtual ground input nodes 180, 182 of the differential amplifier150 to ensure that the switching does not impair performance of theDACs.

[0030] When the outputs of a DAC are switched to the throwaway node, theoutputs are effectively shorted together. Due to the differential natureof the glitch, the glitch elements associated with the shorted DACoutputs tend to cancel each other out. Even if the glitches are notcanceled out, however, any residual glitch is re-directed to thethrowaway node instead of the differential amplifier inputs.

[0031] In one embodiment, differential amplifier 150 is a class Aamplifier. The output of the differential amplifier may be coupled to asubsequent power amplification stage, if necessary. The poweramplification stage might be a class AB amplification stage, forexample.

[0032] In an alternative embodiment, differential amplifier 150 performsthe function of differential current-to-voltage conversion and poweramplification. The use of a class AB amplification stage at this pointeliminates the need for a subsequent power amplification stage. In thepreceding embodiment with independent stages, the input of the class ABamplification stage is buffered from the switching circuitry by theclass A amplification stage. When the functions of differentialcurrent-to-voltage conversion and power amplification are combined intoa single stage, however, the input of the class AB amplification stageis coupled directly to the switching circuitry without the benefit of abuffering class A amplification stage.

[0033] When the DACs, differential current-to-voltage converting poweramplifier, and switching circuitry are located within the sameintegrated circuit, clock signals within the integrated circuit mayinteract with the power amplifier circuitry to produce an amplitudemodulated (AM) version of the clock signals that appears at the DAC andthe current-to-voltage converting power amplifier interface.

[0034] When this AM signal is present in a system switching between twoDACs, the AM signal can be demodulated by the switching action at theoutput of the DACs. This demodulation produces an extraneous basebandsignal that is a distorted version of the true baseband signal producedby the DAC. The introduction of the extraneous signal producesundesirable harmonic distortion at the output of the power amplifier.The harmonic distortion can significantly impair the ability to reliablytransmit data.

[0035] If the DAC outputs were driven by ideal current sources, thecircuitry of FIG. 1 should be immune to clock noise appearing at inputnodes 152 and 154 of the current-to-voltage amplifier 150. The outputimpedance of each output line, however, is finite and typically can bemodeled as a ground connected capacitor. As a result of the commutationof switches 112-118 and 132-138, nodes 152 and 154 are effectivelypresented with a switched capacitor resistance between each of nodes 152and 154 and signal ground.

[0036] If there is any clock noise appearing at nodes 152 and 154 thatis correlated to clock signals φ₁ and φ₂ then the clock noise can bedown converted by the synchronous switching to produce undesirablebasedband signals. These baseband signals add to the DAC output signals(nodes 180, 182 connected to nodes 152, 154, respectively). Aspreviously indicated, the clock signals φ₁ and φ₂ are derived from themaster clock signal such that there is a correlation between φ₁ and φ₂and the clock noise at nodes 152 and 154.

[0037] Thus if the interaction of the master clock signal with the DACs,ground, power supplies, or semiconductor substrate is dependent upon thevoltage signal appearing at the output of amplifier 150, then anamplitude modulated (AM) clock signal can appear at the inputs 180, 182of amplifier 150. The action of switches 112-118 and 132-138 can thendemodulate the AM signal which will result in deleterious effects on thedata attempting to be sampled or communicated.

[0038]FIG. 2 illustrates buffer circuitry for the current-to-voltageconverting amplifier 250. The DACs are coupled through the switchingcircuitry to buffer circuitry input nodes 252 and 254 (corresponding tonodes 152, 154 of FIG. 1). The buffer circuitry is connected to theamplifier input nodes 280, 282.

[0039] Cascode connected metal oxide semiconductor field effecttransistors (MOSFETs) M1 and M2 buffer the input nodes from thecurrent-to-voltage converter 250. The I_(CAS) current sources 210, 220,230, and 240 bias transistors M1 and M2 so that the current signals fromthe DACs may be communicated without distortion or offset. If offsetsare not important or even desired, biasing current sources 230 and 240may be eliminated in an alternative embodiment.

[0040] The advantage of this buffer circuitry is that the clock noiseappearing at amplifier input nodes 180 and 182 is buffered from theswitching circuitry of FIG. 1 thus reducing the effects of anydemodulated AM signals.

[0041] One disadvantage of this approach is that the current sources210-240 must have greater output capabilities than the maximum currentoutput capability of either DAC. Referring to FIG. 1, current sources210-240 must each exceed the I_(DC) current sources 160, 162 associatedwith each DAC. Such large current sources tend to introduce noise intothe digital-to-analog conversion circuitry.

[0042] Another disadvantage becomes apparent for significant signalswings. Even if adequate drive current is supplied by the I_(CAS)current sources, there may be significant signal swings at the drains ofM1 and M2. These signal swings are embodied as voltage swings at thesource of M1 and M2. The sources, however, are coupled to nodes 252 and254 which are in turn coupled (through the switch circuitry) to theoutput of the DACs. The performance of some DACs is adversely affectedby significant voltage swings at the output nodes of the DAC. Thus thebuffering circuitry is adequate only for small signal swings dependingupon the DAC architecture.

[0043] Although feedback circuitry may be used to improve theperformance of the buffer circuitry, the feedback circuitry adds morecomponents and complexity and may reduce the operating bandwidth of thebuffer circuitry and hence the DACs.

[0044]FIG. 3 illustrates improved switching circuitry for the dual DACsystem. Each DAC has a first and a second output. In one embodiment, theDACs are current steering DACs. The eight switches of FIG. 1 arereplaced with two switches.

[0045] The first output of DAC1 310 is coupled to a first switch node352. In the illustrated embodiment, the first switch node 352 isconnected to a first differential amplifier 350 input node 380. A secondoutput of DAC2 330 is coupled to a second switch node 354. In theillustrated embodiment, the second switch node 354 is connected to thesecond differential amplifier input node 382. The second output of DAC1is coupled to the first output of DAC2 at a common node 370.

[0046] Switch 332 couples the common node to the first switch node 352in response to switch signal φ₁. When switch signal φ₁ is asserted,switch 332 also effectively shorts the outputs of DAC2. DAC2 may beupdated while switch signal φ₁ is asserted.

[0047] Switch 312 couples the common node 370 to the second switch node354 in response to switch signal φ₂. When switch signal φ₂ is asserted,switch 312 also effectively shorts the outputs of DAC1. DAC1 may beupdated while switch signal φ₂ is asserted.

[0048] The waveforms of the switch signals are out-of-phase so that theactive regions of φ₁ and φ₂ do not overlap each other. Thus only one ofswitches 312 and 332 is closed at any given time. As with FIG. 1, a twophase clock configured so that the active regions of φ₁ and φ₂ do notoverlap may be used to generate switch signals φ₁ and φ₂.

[0049] During the assertion of φ₁, DAC1 310 has its outputs coupled tothe inputs of current-to-voltage converting amplifier 350. At the sametime the inputs for DAC2 330 are shorted together. As long as the DACsare designed such that the sum of their respective output currents issubstantially constant, the circuitry functionally performs the same asthat of FIG. 1. When φ₂ is asserted, the outputs of DAC1 are shortedtogether and the outputs of DAC2 are coupled to the current-to-voltageconverting amplifier. The circuitry of FIG. 3 tends to eliminateglitches by coupling a given DACs outputs together. Due to thedifferential nature of the glitch, the glitch elements associated withthe shorted DAC outputs tend to cancel each other out.

[0050] When the components of FIG. 3 reside on a same integrated circuitdie, the DACs and the switches tend to be closely matched. Thus thecurrent, I_(SUM), flowing through switches 312 and 314 is nearly zero orat least small such that I_(SUM)<<I_(DC). Given that the switches ofFIG. 3 are required to carry a fraction of the current of the switchesof FIG. 1, switches 312-318 and 332-338 can be fabricated usingconsiderably smaller components. The smaller size saves space in anintegrated circuit and tends to reduce clock feedthrough associated withthe switches.

[0051] The digital inputs presented to DACs 310 and 330 are likely thesame or close. The DACs are receiving the same data with perhaps a halfclock cycle skew. The maximum difference in output values between DAC1and DAC2 is related to the maximum code-to-code deviation in theincoming data. Typically, the maximum code-to-code deviation issignificantly less than full scale.

[0052] The input codes for oversampling converters, for example, changeat a fraction of the Nyquist frequency of the DAC. The code-to-codetransitions for oversampling converters are guaranteed to be very small.Thus the I_(SUM) of FIG. 3 will be considerably smaller than the I_(DC)of FIG. 1.

[0053] One disadvantage of the circuitry of FIG. 3 is that the switchesare directly coupled (i.e., without buffer circuitry) to the amplifierinput nodes 380 and 382 at nodes 352 and 354. As a result, the circuitrymay experience the same AM demodulation of clock noise with thecorresponding deleterious effects particularly if differential amplifier350 is a class AB amplifier.

[0054]FIG. 4 illustrates another embodiment of a dual DAC system. Thesimplified switching circuitry of FIG. 3 is combined with the buffercircuitry of FIG. 2. Given that the signal swings experienced by I_(SUM)are very small and that I_(SUM) is nearly zero, the current sourcesI_(CAS) do not require the capability of generating currents that canexceed I_(DC).

[0055] The DACs (410, 430) are coupled through the switching circuitryto buffer circuitry input nodes 452 and 454. The buffer circuitry isconnected to the input nodes 480, 482 of current-to-voltage convertingamplifier 450. As with FIG. 2, the input nodes 480 and 482 of amplifier450 are isolated from the switches 412 and 432 by the buffer circuitry.As a result of the decreased current carrying requirements switches 412and 432 can be fabricated much smaller than the switches 112-118 and132-138 of FIG. 1. As a result, the switching circuitry of FIG. 4 canoperate at a higher switching rate than the switching circuitry of FIG.1.

[0056] The circuitry of FIG. 4 includes level shifting circuitry 490 forthe common node 472. The expanded view of level shifting circuitry 490illustrates the detailed connections of a diode coupled MOSFETtransistor M3 to nodes 470 and 472.

[0057] The purpose of M3 is to enable matching the voltage across eachI_(DC) current source (e.g., 460) to the voltage at the differentialamplifier input nodes 480 or 482 (V₄₈₀≈V₄₈₂ as a result of the virtualground at the differential amplifier inputs). Each DAC can be modeled ashaving a capacitor parallel to its associated current source. As theI_(DC) current is steered to I₁₁ or I₁₂, for example, sudden variationsin the voltage across this capacitor can affect the operation of theDAC. To avoid this undesirable operation, the voltage at node 472 ismaintained at the same voltage as node 480 through the use of M3.V_(REF) is also maintained at V₄₈₀.) Diode connected transistor M3 andcurrent sources I_(CAS2) (I_(CAS2)<I_(CAS)) co-operate to level shiftnode 472 such that V₄₇₂≈V₄₈₀.

[0058]FIG. 5 illustrates one application for the digital-to-analogconversion circuitry. The circuitry is illustrated in functional blockform. An analog front end 580 is used to drive a telephone subscriberline including the tip 582 and ring 584 lines. Modems such as digitalsubscriber line modems are an example of such an application.

[0059] The DACs 510, 530, switching circuitry 540, and differentialamplifier 560 are fabricated on a common semiconductor die 590. In theillustrated embodiment, the analog front end 580 includes a two phaseclock generating circuit 520 and buffer circuitry 550 on the samesemiconductor die. A power amplifier 570 is also included on the samedie.

[0060] Buffer circuitry 550 permits the use of class A or class AB typedifferential amplifier stage 560. In the event that differentialamplifier 560 is a class A amplifier, buffer circuitry 550 may beeliminated. Similarly, if the differential current-to-voltage conversionand power amplification functions are combined into a singleamplification stage, then the subsequent power amplifier stage 580 maybe eliminated.

[0061] The output of the power amplification stage may be coupled to thesubscriber line through interface circuitry 586 external to theintegrated circuit package, if necessary. Thus in one embodiment, theDACs, switching circuitry, differential amplifier, power amplifier, andbuffer circuitry share a common semiconductor substrate within the sameintegrated circuit package. These components may thus collectively befabricated on the same integrated circuit die 590. In one embodiment,the integrated circuit die is a complementary metal oxide semiconductor(CMOS) integrated circuit die.

[0062] In the preceding detailed description, the invention is describedwith reference to specific exemplary embodiments thereof. Variousmodifications and changes may be made thereto without departing from thebroader spirit and scope of the invention as set forth in the claims.The specification and drawings are, accordingly, to be regarded in anillustrative rather than a restrictive sense.

What is claimed is:
 1. A circuit apparatus for performingdigital-to-analog conversion, comprising: first and seconddigital-to-analog converters (DAC), each having a first and a secondoutput, wherein the second output of the first DAC is coupled to thefirst output of the second DAC at a common node, wherein the firstoutput of the first DAC is coupled to a first switch node, wherein thesecond output of the second DAC is coupled to a second switch node; afirst switch for coupling the common node to the first switch node; anda second switch for coupling the common node to the second switch node.2. The apparatus of claim 1 wherein each DAC provides a differentialoutput signal in response to a given input, wherein a sum of the firstand second outputs of each DAC is substantially constant independent ofany input.
 3. The apparatus of claim 1 further comprising: adifferential amplifier, wherein the first switch node is coupled to afirst input node of the differential amplifier, wherein the secondswitch node is coupled to a second input node of the differentialamplifier.
 4. The apparatus of claim 3 wherein the differentialamplifier is one of a class A and a class AB amplifier.
 5. The apparatusof claim 3 wherein the differential amplifier is a current-to-voltageamplifier.
 6. The apparatus of claim 1 wherein the first switch couplesthe common node to the first switch node in response to a first switchsignal, wherein the second switch couples the common node to the secondswitch node in response to a second switch signal.
 7. The apparatus ofclaim 6 wherein active regions of the first switch signal do not overlapactive regions of the second switch signal such that the common node iscoupled through the first and second switches to only one of the firstand second switch nodes at any given time.
 8. The apparatus of claim 1wherein the first and second DACs and the first and second switches arefabricated on a same semiconductor substrate.
 9. The apparatus of claim1 further comprising: a buffer circuit, wherein the first switch node iscoupled to a first buffer input node of the buffer circuit, wherein thesecond switch node is coupled to a second buffer input node; and adifferential amplifier, wherein a first buffer output node of the buffercircuit is coupled to a first input node of the differential amplifier,wherein a second buffer output node of the buffer circuit is coupled toa second input node of the differential amplifier, wherein the buffercircuit substantially isolates the first and second input nodes of thedifferential amplifier from any noise at the first and second switchnodes.
 10. The apparatus of claim 9 wherein the first and second DACs,the first and second switches, the buffer circuit, and the differentialamplifier are fabricated on a same integrated circuit die.
 11. A methodof performing digital-to-analog conversion, comprising the steps of: a)providing a first and a second digital-to-analog converter (DAC), eachhaving a first output and a second output, wherein the first output ofthe first DAC is coupled to a first switch node, wherein the secondoutput of the second DAC is coupled to a second switch node, wherein thesecond output of the first DAC is coupled to the first output of thesecond DAC at a common node; b) coupling the common node to the secondswitch node in response to a first switch signal; and c) coupling thecommon node to the first switch node in response to a second switchsignal.
 12. The method of claim 11 wherein the first and second switchsignals have waveforms with non-overlapping active regions such that thecommon node is coupled through the first and second switches to only oneof the first and second nodes at any given time.
 13. The method of claim11 further comprising the step of: d) updating the first DAC while thesecond switch signal is active.
 14. The method of claim 11 furthercomprising the step of: d) updating the second DAC while the firstswitch signal is active.
 15. The method of claim 11 further comprisingthe step of: d) providing a differential amplifier having input nodesconnected to the first and second switch nodes.
 16. The method of claim11 further comprising the steps of: d) providing buffer circuitry; ande) providing a differential amplifier, wherein input nodes of thedifferential amplifier are coupled to the first and second switch nodesthrough the buffer circuitry, wherein the buffer circuitry substantiallyisolates the differential amplifier input nodes from noise at the firstand second switch nodes.
 17. A digital-to-analog conversion circuitapparatus, comprising: first and second digital-to-analog converters(DAC), each having a first and a second output, wherein the secondoutput of the first DAC is coupled to the first output of the second DACat a common node, wherein the first output of the first DAC is coupledto a first switch node, wherein the second output of the second DAC iscoupled to a second switch node; a first switch for coupling the commonnode to the first switch node; and a second switch for coupling thecommon node to the second switch node, wherein the DACs and switches areformed on a same integrated circuit die.
 18. The apparatus of claim 17further comprising: a buffer circuit; and a differential amplifier,wherein a first input node and a second input node of the differentialamplifier are coupled to the first and second switch nodes,respectively, through the buffer circuit, wherein the buffer circuitsubstantially isolates the first and second input nodes of thedifferential amplifier from any noise at the first and second switchnodes, wherein the buffer circuit and differential amplifier are formedon the integrated circuit die.
 19. The apparatus of claim 17 wherein theDACs are current steering DACs.
 20. The apparatus of claim 17 whereinthe integrated circuit die is a complementary metal oxide semiconductorintegrated circuit die.
 21. The apparatus of claim 17 furthercomprising: a two phase clock providing a first clock signal to controlthe first switch and a second clock signal to control the second switch,the two phase clock formed on the integrated circuit die, wherein firstand second clock signals have distinct phases to ensure that the commonnode is coupled to only one of the first and second switch nodes at anygiven time.
 22. A digital-to-analog conversion circuit apparatus,comprising: a first and a second digital-to-analog converter (DAC); andswitch circuitry coupling a selected output of only one of the first andsecond DACs to an output node at any given time.
 23. The apparatus ofclaim 22 wherein the switch circuitry is controlled by switch controlsignals independent of any DAC input data.
 24. The apparatus of claim 23wherein the switch circuitry periodically alternates between couplingthe selected output of the first DAC and the selected output of thesecond DAC to the output node.
 25. The apparatus of claim 23 furthercomprising: a throwaway node, wherein the switch circuitry couples theoutputs of the second DAC to the throwaway node when coupling theoutputs of the first DAC to the output nodes, wherein the switchcircuitry couples the outputs of the first DAC to the throwaway nodewhen coupling the outputs of the second DAC to the output nodes.
 26. Adigital-to-analog conversion circuit apparatus, comprising: a first anda second digital-to-analog converter (DAC); and switch circuitry forcoupling a differential output of a selected exclusive one of the firstand second DACs to a pair of output nodes.
 27. The apparatus of claim 26wherein the switch circuitry is controlled by switch control signalsindependent of any DAC input data.
 28. The apparatus of claim 27 furthercomprising: a multiphase clock for controlling the switch circuitry totime interleave the differential outputs of the first and second DACsonto the pair of output nodes.
 29. The apparatus of claim 27 whereinwhen the differential output of the selected DAC is coupled to theoutput node pair, the differential output of the non-selected DAC iscoupled to a throwaway node.
 30. The apparatus of claim 27 wherein theoutput nodes are coupled to a differential amplifier.
 31. The apparatusof claim 30 wherein the differential amplifier is a selected one of aclass A and a class AB amplifier.